ADLINK Technology - ADLINK Technology

Jacka Tsai,
ADLINK Technology

Several applications, such as image data detection, video data compression, audio data gain, and motor control, exhibit the need for improved expandability and data processing speed. Current trends demonstrate a suitable solution in programmable data processing modules. For example, FPGAs are an essential component for image data error correction modules. Firmware engineers can use HDL to code this component with algorithms as required by customers. To add or modify functionality, simply change the HDL code and write it to the FPGA chip. Hardware cards do not need to be reworked or redesigned.

As the amount of data processed increases, the amount of memory needed also increases. FIFOs of the past are unable to meet such speed and capacity requirements. Many firmware engineers now consider DRAM as the likely choice for such applications. DRAM offers high-speed access and the ability for designers to define space and capacity to be used. However, DRAM requires re-charging. Even DDR SDRAM requires data phase synchronization, which is much more difficult to design with than a FIFO. Thus, designing around a FPGA chip with its RAM control IP from the supplier, in conjunction with control logic developed by firmware engineers is the current trend in data control access.

The purpose of this article is to propose the idea of adding a wrapper to DRAM control IP to essentially make it a FIFO interface to form a multi-port memory access (MPMA) technology, combining large capacity and fast access time of the DRAM with the ease of use of the FIFO interface. During the design process, DRAM space can be used as needed, thus offering a greater amount of flexibility. The DRAM used has two write ports and two read ports, as shown in Figure 1. The data at each write port can be continually written from the first address to the last address. Data writes start again at the first address, forming a circular write mode. The read method for each read port behaves similarly as the write ports. As long as the amount of data being written to memory exceeds the amount being read, it conforms to a FIFO class of access methods.

Figure 1. DRAM control port with two write and two read ports.

How to use MPMA in data processing modules

Most high-capacity data processing applications require a large amount of data registers. Yet for the price of a 4 kB FIFO, 32 MB DRAM chips can be purchased; offering more than ample memory space. However, as mentioned, access control for DRAM is quite complex. The HDL calculations to write to a FPGA can only be done by the manufacturer's proprietary IP. Figure 2 shows the proprietary DRAM control IP within a FPGA.

Figure 2: DRAM control IP used for data access

Some applications include processing a large amount of repeating data. As shown in Figure 3, to detect if P4 is inaccurate, image error detection processing is used on eight neighboring primary image data points as reference data for comparison. If a FIFO is used, it's likely not possible to store three lines of data in its registers. Using DRAM offers ample registers to access a such a large range of data.

Figure 3. Primary image data matrix

Because DRAM control is complex, the desired data address must be recalculated at each access. Depending on the continuity of its data address, once the primary image data has been written, three ports can be used as continual addresses for reading. For example, in Figure 3, the first port continually reads P0, P1, and P2; the second port continually reads P4, P5, and P6; and the third port continually reads P8, P9, and P10 to detect errors in P5. When determining if there is an error at P6, the first, second, and third ports need to only read P3, P7, and P11, respectively, to form a complete calculation with the previous data. This greatly improves data usability. Also, due to the continuous reading mechanism and as long as each port reads the data in a continuous manner, the following data address do not need to be calculated over and over; significantly simplifying DRAM control.

MPMA Technology Introduction

For example, the Altera MegaCore IP generator was used to generate a DDR DRAM controller. Then, wrapper logic was also created and added to the project to form a FIFO MPMA port (32 bits in, 8 bits out). Figure 4 is a block diagram of the system.

Figure 4. FIFO MPMA access port.

64-bit data buses are used between the Altera DDR DRAM controller and the write and read wrappers to provide ample bandwidth for read and write operations. Progress accumulation is used to calculate the data addresses within the write/read wrapper. Its access interface is very similar to a FIFO unit in regards to simplicity, yet still able to support large amounts of data.

Each wrapper contains a small FIFO, a packing/unpacking mechanism, and an address progression counter. The FIFO is used to adjust the different settings between the user interface and DRAM clock domain. The packing/unpacking mechanism is used to regulate the input/output interface bus width to correlate with the DRAM control IP interface to effectively write and read DRAM data. The address progressive counter is the DRAM address generator for each wrapper. When the counter number written to the wrapper is greater then the counter read from the wrapper, the data to be read must be legal data already written to the DRAM, or else the incorrect data will be accessed.

Efficiency by using MPMA

Using P5 from Figure 3 as an example, if a wrapper was not used, P5 would have been written once, but read nine times (once as the primary calculation point and eight times as a reference point). For an image with n points of data, which would require error detection processing, there will be n*(1+1+8) times of data access. Latency issues would also occur during address calculation.

When using a 1-in, 3-out MPMA wrapper, the same P5 point only needs to be written once and read three times (each of the three read wrappers read it once). For the same n number of points, error detection processing can be accomplished with only n*(1+3) number of accesses. In addition, the latency issue is overcome by the DRAM's progression addressing. This simple calculation shows that MPMA designs can improve data access efficiency by a factor of two.

Conclusion

As applications grow more complex and the amount of data written and read increases, tradition FIFOs are not able to keep up with increasing capacity and speed demands. DRAM offers the capacity required, but its difficult control logic and access control create an enormous bottleneck for the system.

The presented method of utilizing a write/read wrappers around the FPGA manufacturer's IP core accomplishes the benefits of a high capacity and simple FIFO-like interface operations. Users can define the bus width of each write/read port of the MPMA wrapper to further control calculation time efficiency.

ADLINK Technology is continually developing products and refining technologies for the field of control automation. ADLINK Technology applies such technology to high data volume image capture/processing modules to offer the benefits of high-volume image data transmission.

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