Technology is always improving to meet the needs of applications. Product designers must stay a step ahead of design changes. Traditional IPCs are primarily composed of a SBC and backplane integrated with PCI/ISA gold finger connecters and slots. Most early 4U style chassis had 4 PCI slots and 8-12 ISA slots-obviously concentrating on ISA expansion slots. As the mainstream shifted from ISA to PCI, the need for additional PCI slots on the backplane escalated. Thus, PCI-to-PCI bridges found a new home. In other markets, Eurocards, used by telecoms, were originally designed around the VME Bus, which followed the same plight as ISA and was slowly replaced by PCI, giving birth to the CompactPCI architecture. Because the Eurocard architecture also requires several slots, CompactPCI SBC and backplane designs started considering using PCI-to-PCI bridges.

Most SBC applications fall into two areas: host CPU and peripheral CPU. Both of these applications require a PCI-to-PCI bridge to connect the CPU card to the PCI bus on the backplane. The only difference is if the CPU card is inserted as the system host CPU or on the side as a peripheral CPU, the bridge will be different: transparent or non-transparent. The following is a thorough evaluation of applications of bridges on SBCs, backplanes, and the CompactPCI (especially design). Additionally, there is a short introduction on the technological development trends of PCI-to-PCI bridges.

Traditional IPCs can be broken down into two parts: the SBC and backplane (as shown in Figure 1). Backplanes must be designed in accordance to the PICMG 1.0 specifications. In Figure 1, you can see the two PCI-to-PCI bridges on the 10-slot backplane. The CPU card would have to produce the following signals to utilize the four expansion slots (PCI bus 0) if pre-PCI-to-PCI bridge specifications are used:

• 1. REQ(3,2,1,0)#
• 2. GNT(3,2,1,0)#
• 3. The clocks of Slot(1,2,3,4) are connected to CLK(A,B,C,D), respectively
• 4. IDSEL signals of Slot(1,2,3,4) are connected to AD(31,30,29,28), respectively
• 5. Interrupt INT(A,B,C,D) routing is connect by the PCI specifications using defined routing rules

To increase the number of expansion slots, place two PCI-to-PCI bridges (PCI bridge specification compliant) in slots 3 and 4. Each bridge supports 8 PCI slots (PCI buses 1 and 2), bringing a total of18 available slots on the backplane. Additional REQ#, GNT#, and CLK signals are produced by the bridge. The four interrupts INT(A,B,C,D) must be connected according to PCI-to-PCI bridge specifications so that they can be shared between the three buses (PCI buses 0, 1, and 2).

Figure 1. 4U Chassis, PICMG SBC, and 18-slot PCI backplane

Through PCI-33MHz simulation and testing, CompactPCI specification PICMG 2.0 restricts the number of slots to 8 or less. In order to design for 8 slots, the CompactPCI SBC must use a PCI-to-PCI bridge. The expanded PCI bus signals connect the SBC's J1 and J2 to P1 and P2 on the backplane, and then are distributed to each slot (see Figure 2). Except for the system slot, the signals for the remaining 7 slots on a CompactPCI backplane must follow the following design specifications:

• 1. REQ(6,5,4,3,2,1,0)#
• 2. GNT(6,5,4,3,2,1,0)#
• 3. The clocks of Slot(1,2,3,4,5,6,7) are connected to CLK(A,B,C,D,E,F,G), respectively
• 4. IDSEL signals of Slot(1,2,3,4,5,6,7) are connected to AD(31,30,29,28,27,26,25), respectively
• 5. Interrupt INT(A,B,C,D) routing is connect by the PCI specifications using defined routing rules

Figure 2. 3U and 6U SBCs and 8-slot backplanes

If up to 15 slots are desired, then designers must follow the PICMG 2.7 specifications and the SBC must have two PCI-to-PCI bridges (see the block diagram of Figure 3 for a general depiction). Additionally, the backplane design must expand Bus A via P1 and P2 to slots 1-7 through the first bridge, and Bus B via P4 and P5 to slots 9-15 through the second bridge (see Figure 4).

Figure 3. 6U SBC, dual-bridge design

Figure 4. 6U 15-slot, dual-system board

In the previous section, we used the bridge on the CPU card to expand backplane slots. However, sometimes the CPU board has restricted surface area, or J4 and J5 are already used for other purposes leaving no choice but to place the other bridge on the backplane. However, if the backplane happens to NOT have the required space, then the design cannot be as simple as the typical backplane shown in Figure 1.

For such a case, there is a versatile solution: place the bridge on a daughter board. This daughter board connects to one of the 7 slots of the primary bus to one of the (up to 7) expansion slots on the secondary bus via the back side of the backplane (see Figure 5). This type of configuration is common on 3U systems because its J4 and J5 are not useable. 6U systems, on the other hand, frequently use the method shown in Figure 4.

Figure 5. Pallet Bridge Method

Most CompactPCI systems are used as a host computer just like typical PCs. However, several unique applications are best fitted with a peripheral CompactPCI card with the computing power of a standard CPU card. In order to achieve this, PCI-to-PCI non-transparent bridges were born. PCI-to-PCI non-transparent bridges separate the backplane's PCI bus from the peripheral CPU card's PCI bus; even though the two different CPU cards are connect to the same PCI bus.

What, exactly, are PCI-to-PCI non-transparent bridges? How can they be employed? Below is a brief explanation:

For an example, we used the Intel 21555 non-transparent bridge in the ADLINK cPCI-6765 6U CompactPCI peripheral CPU card (see Figure 6).

Figure 6. Intel 21555 non-transparent bridge and ADLINK cPCI-6765 peripheral CPU card

The ADLINK cPCI-6765 is specifically designed to be used in a CompactPCI peripheral slot (instead of the system slot). Communication between it and the host slot CPU card is similar to communication between conventional CPUs and peripherals. The CPU card only sees the PCI component containing the 21555 on the PCI bus (see to Figure 7). Drivers running underneath the OS make it possible for the cPCI-6765 board's BIOS to allocate fixed I/O or memory space to store/retrieve data to/from the cPCI-6765 board's actual address. If the host slot CPU needs to access address space on the cPCI-6765, the 21555 will remap the address and the request will be handle through the cPCI-6765. Similarly, the cPCI-6765 only sees the 21555 on the PCI bus and uses the same method to access the host slot CPU card.

Figure 7. CompactPCI host slot and peripheral CPU cards

Over the past few years since the development of the PCI bus, most applications have centralized around the 32-bit/33MHz standards. During that time, the most popular PCI-to-PCI bridges include: Intel 32-bit transparent 21150 and 21152, the Texas Instrument PCI2050 series, HiNT HB1 and HB2, etc. Most companies focused on making pin compatible bridges. Subsequently, the 64-bit PCI has now become more widespread. Companies like Intel, HiNT, Pericom, etc. are likely to still make pin compatible bridges modeled after the Intel 21154. The ADLINK dual Xeon 6U CPU card (cPCI-6860) is designed using this bridge.

Afterwards, Intel developed the 21554 and followed up with the newly designed 21555 64-bit non-transparent bridge to give x86-based motherboards the opportunity to be used as peripheral cards. Shortly after, HiNT, Intel's competitor, designed the universal bridge HB6 using the same pinout as the 21154, but possessing the same features as the 21555. The HB6 is used in the ADLINK cPCI-6862 dual LV-PIII 6U CPU card-Taiwan's first host/peripheral universal CPU card.

PCI-to-PCI bridges from large manufactures like Intel, HiNT, Pericom, and Texas Instrument employ distinct features with the latest technology. Recently, the trend has shifted towards PCI-X high-end x86-based applications, including products from the above mentioned companies. The competition between Intel and HiNT is especially fierce with their latest PCI-X chips.

PCI-to-PCI bridges, while rarely used in typical PCs, are a vital component of IPCs. As mentioned above, typical IPC backplanes and motherboards or CompactPCI system backplanes and motherboards all include PCI-to-PCI bridges.

ADLINK offers this article to interested parties to share our expertise of designing for PCI-to-PCI bridge applications.