The popularity of x86 based computers in the industrial and Computer Telephony Integration (CTI) markets created a need for passive backplane based systems. Although motherboard based computers have made some inroads into these markets, the limitations of this architecture prevent wide spread adoption. Passive backplane computing is not a new idea. The PCI Industrial Computer Manufacturers Group (PICMG) was established in May of 1994 with the goal of defining a PCI/ISA passive backplane and CPU card interface specification. As we approach the 10 year anniversary of the PICMG based passive backplane compute architecture we find the standard has evolved to meet the ever changing needs of the market.

The development of passive backplane based systems has been driven by the desire to improve the mean time to repair and to provide an easier path for system upgrade. A motherboard based system is inflexible in that requires the replacement of the entire motherboard to repair or update a system. Replacing the motherboard requires that all plug in cards and cables be removed before the motherboard can be removed. This results in increased system downtime for repair or upgrade which is unacceptable in many control and CTI applications. A passive backplane architecture solves these problems by eliminating the motherboard. In a passive backplane system, the CPU is a plug in card. The backplane consists of connectors and passive devices. This architecture makes system upgrades and repairs simple with minimal downtime.

The PICMG 1.0 PCI/ISA Passive Backplane Specification was developed with the challenges of 1994 in mind. This specification supported ISA and PCI plug in cards. It was design for 33MHz 32 bit PCI with a migration to 64 bit PCI. CPUs and backplanes built to this specification could support as many as 20 ISA cards and 4 PCI cards. In this architecture the CPU card can draw power from pins on the ISA and PCI connectors. This avoided the maximum power available in the PCI local bus specification. In defining the pinout for passive backplane CPU cards had to include signals that were not normally found on PCI plug in cards. The additional signals included 4 request/grant pairs for bus arbitration, 4 clocks for the supported 4 PCI slots as well as a reset output. One other challenge was the interrupt and IDSEL assignments. In a motherboard environment the system BIOS knows the mapping relationship between the plug in slots, IDSEL and interrupt assignments as they are all part of the motherboard. In a passive backplane environment the IDSEL and interrupt routings are a part of the backplane routing. The specification needed to define the relationship of these signals so that compatibility between CPU card vendors could be achieved. An example of a PICMG 1.0 SBC is shown below.

Figure 1 ADLINK NuPro-842 PICMG 1.0 Compliant Single Board Computer

The industrial and computer telephony integration markets were slow to migrate from ISA to PCI based I/O cards. As a result, the PCI-ISA specification is still in use today. In 2002 PICMG developed an all PCI version of the PICMG 2.0 PCI-ISA specification that included PCI-X support. This new specification is PICMG 1.2 Embedded PCI-X Specification. This specification kept the same physical size of the PICMG 1.0 PCI-ISA specification but replaced the ISA bus with a second PCI bus. In addition PICMG 1.2 added support for PCI-X protocol. Board, and support for an ATX style power connector to power high performance processors. This specification also defined a new name for the plug in CPU card, System Host Board (SHB). The SHB provides clocks and arbitration for the backplane slots. An SHB can be full length or half length and can support one or two PCI interfaces. An example of a ePCI-X SHB is shown below.

Figure 2 ADLINK NuPro-900 PICMG 1.2 Compliant SHB

With the addition of PCI -X the length of the clocks on the backplane became critical. The authors of the specification wanted to define SHBs that would interoperate with a variety of backplanes. The challenge is that the PCI-X interface on the SHB requires a feedback clock that has a delay equal to the trace length of the clocks on the backplane. The solution was to define a feedback clock. The feedback clock is on the backplane and its length is based on the length of the clocks from the SHB slot to the PCI plug in card slots. In the drawing below, the clock distance from the Bridge to any of the three destinations is the same length.

Clock Routing for PICMG 1.2

The passive backplane as evolved along with the primary markets it addresses. The PCI Industrial Computer Manufacturers Group was established to define an industrial PCI/ISA passive backplane and CPU card interface specification. The specification PICMG 1.0 was released in 1994. The PCI/ISA passive backplane specification was later supplemented with PICMG 1.2 Embedded PCI-X. The PICMG 1.2 specification removed the ISA connections and added a second set of PCI connections as well as an ATX style power connector for high performance processors. Passive backplane architectures continue to be popular in application where minimizing down time is important.