Although the size of microprocessors and peripherals has stayed somewhat constant over the years, there is an area that has been expanding rapidly - system memory. The low cost of DRAM coupled with the high performance of today's processors has dramatically increased the memory requirement of CompactPCI processor boards. Most vendors support one or two gigabytes of memory on single slot CompactPCI boards. This memory is typically supported using on-card mounted DRAM and expansion through a SO-DIMM socket. Next generation designs will require four to eight gigabytes of memory. With typical SDIMM densities around 2GB, one would have to cover a CompactPCI board with DIMM sockets to fit 8GB of memory. Designers of next generation boards will need to find ways to put down 38 or more DRAMs on a CompactPCI board and still provide the rich set of peripherals customers expect. Memory chip densities of 512Mb and 1Gb will necessary. The challange with board size will be to place and route the memory devices while meeting the timing requirements for high speed memory. This is achievable but will take more planning and longer design cycles then have been required in past designs.

X86 processors have gone through a significant change over the life of CompactPCI. Some of the very early processor boards had 66MHz CPUs. The current generation of x86 products contain 1.7GHz mobile Pentium 4 CPUs. The embedded industry's need for long life cycle support has required manufacturers to select processors from embedded or long life supported roadmaps. These products are not as leading edge as desktop or server processors but they have life cycles that are measured in years not months. In addition, the industry has also been able to take advantage of mobile processors that have power requirements much similar to embedded and telecommunications applications. The graph below provides an indication of the amount of power various families of the Pentium processor dissipate. As you can see, Pentium III and Mobile Pentium 4 processors families have processors that can fall within the 30 Watt budget that today's CompactPCI boards have for processors.

As we look to future x86 designs we can see that CompactPCI board designs will need to support processors that are approaching 60 and even 80 Watts of power dissipation. Solving this problem will require improved heatsink designs and better thermal management. The ability of the board and mechanical designers to work together to solve the thermal challenges will be very important in next generation designs.

CompactPCI boards receive power through the J1/J2 connectors. There are 8 3.3V, 6 5V, 1 +12V, and 1 -12V power pins. These pins are rated at 1Amp based on the IEC 61076-4-101 specification. The 1 Amp per pin limit is conservative and somewhat misleading in that it allows for all pins to draw 1 Amp of current at an ambient temperature of 70oC. In reality, not all pins in the connector are loaded to the maximum current rating. In fact, most of the CompactPCI pins are trying current that is in the milliamp range. The 1 Amp limit at 70oC is based on the amount of heat that is generated as current flows through the pin. As you increase the current, you increase the voltage dropped across the pin. Since the heat generated is a function of voltage and current, the increase in the current and voltage increase the temperature of the connector pin. In CompactPCI the only pins that draw any significant amount of power are the power supply pins. If the designer was to assume that every other pin in the J1/J2 connector carried power then the maximum current per pin would be 2.5 Amps at 40oC. This information can be found in chapter 4.2.3 of the IEC 61076-4-101 specification. The amount of power available to the board based 2.5 Amps per pin is shown in the table below.

The table above shows that board designers can draw up to 200 Watts of power through the J1/J2 connectors. Designers do need to take care not to exceed the power rating for any individual supply voltage. Typical DC-DC converts used to generate the CPU core voltage run off +12V. Even with the increased current rating the amount of power available on +12V is probably not sufficient for next generation processors. Designers will need to take care to balancing the use of the input voltages as to not exceed the maximum power for an individual supply. From a user standpoint care needs to be taken to ensure that the total amount of power required for all boards in a system does not exceed the system's ability to deliver power. Check the recommended power rating of the power supplies used to ensure that the load does not exceed the available power.

Removing the power (heat) that a CompactPCI board generates is the most significant challenge. Forced air is the typical method used to remove heat and cool a board. At first glance, one might expect that increasing the airflow over a heatsink or increasing the heatsink size could solve any thermal problem. The reality is that there are limits to the effectiveness of forced air cooling and to the impact that increasing the size of the heatsink might have. Most CompactPCI boards have PMC (PCI Mezzanine Card) sites or memory modules that limit the size of the thermal solution. In addition, the heat generated by a processor is concentrated in a small area. Increasing the size of the heatsink does not offer a linear reduction in the amount of heat that the heatsink can dissipate. Another factor is the ability of a heatsink to dissipate power and is called its Thermal Resistance. The Thermal Resistance is given in oC/W and when multiplied by the amount of power to dissipate provides the rise in temperature over ambient that can be expected. As an example the temperature of a processor that dissipates 40 Watts of power with a heatsink that has a Thermal Resistance of .5oC/W will be 20oC above the ambient temperature. The graph below provides a general indication of the Thermal Resistance, heatsink size and airflow. It should be noted that the x and y axis of the graph are logarithmic. As you can see from the graph, the ability of a heatsink to dissipate power is not a liner function of the airflow. A significant improvement in the Thermal Resistance can be seen between convection airflow and 500 ft/min of forced air. The improvement in Thermal Resistance from 500 ft/min to 1,000 ft/min is not as dramatic.

Another factor and limitation in forced air cooling is acoustic noise. The amount of noise generated as the forced air passes through the board and heatsink increases as the speed of the forced air increases. From a practical standpoint, most CompactPCI chassis provide a maximum of 300 ft/min of forced air. As mentioned earlier, the size of the heatsink is generally limited by PMC sites and memory mezzanines. A CompactPCI board that contains two PMC sites will have a microprocessor heatsink that is approximately 3 in x 4.5 in x .7 in or 9.45 in3 that would have a Thermal Resistance of .62oC/W with 300 ft/min of forced air. Most processors have a maximum case temperature of 70oC. The maximum ambient temperature for embedded applications can easily be 50oC. Given all this information the maximum power that a microprocessor can dissipate while meeting the thermal limitations can be calculated by the formula:

Maximum Case Temperature = Thermal Resistance * Power + Ambient Temperature
(Maximum Case Temperature - Ambient Temperature)/Thermal resistance = Power
(70oC - 50oC)/.62oC/W = Power = 32 Watts

A 32 Watt power budget allows us to support Pentium 4 class processors up to 1.7Ghz. To increase the processor speed we will need to increase the heatsink size, reduce the maximum operating temperature, increase the airflow or some combination of all the above. A target for next generation design might be sub 3GHz Pentium 4 processors. For this, we will need to be able to dissipate 65 Watts of processor power. Our next generation board will be feature rich so we are not able to increase the size of our processor heatsink. We will need to dissipate the additional 33 Watts of power by increasing the airspeed and reducing the maximum operating temperature. At 450 ft/min of forced air the Thermal Resistance of our heatsink is .45oC/W. The ambient operating temperature could be reduced to 40oC. Given these changes, the maximum amount of processor power would be:

(70oC - 40oC)/.45oC/W = Power = 66 Watts

At 66 Watts we are just in our power budget. These calculations show that it is possible to increase the power of the processor by changing the airflow and temperature specifications. It should be noted that the Thermal Resistance numbers listed will vary based on the heatsink attachment method. Another consideration is that the processor heat is typically generated in the center of the package and not spread evenly over the heatsink further reducing the efficiency. Thermal simulations will need to be performed to validate the thermal solution. Users of next generation boards will need to ensure that the chassis being used can provide the amount of airflow required to keep the processor within its specification.

Designers and users of next generation x86 technologies will need to pay more attention to the intricacies in the design and integration. It is clear that the challenges posed can be overcome. Designers will need to continue to squeeze more and more silicon onto a fixed size board. Thermal engineers will need to design more efficient heatsinks and the user will need to spend more time ensuring that the boards meet the power and cooling budgets available in the platforms. It would seem that the next generation of x86 processor technology will push CompactPCI to its limits. It is unclear how we will be able to solve the challenges that are a year out; yet that is the same thing the industry thought a year ago. We always seem to be able to find innovative solutions for the challenges that face our industry.